This invention relates to processes for making semiconductor integrated circuits and, particularly, to techniques used for filling relatively small dimension vias.
In the process of forming dual damascene patterns, the back end of the line process of semiconductor manufacturing may use the via first patterning approach. In such a process, an interlayer dielectric may be patterned with a relatively smaller-diameter via than the corresponding metal/trench layer. An anti-reflective coating may then be used to fill the via and to coat the interlayer dielectric for the subsequent trench pattern (for lithographic concerns).
The via fill, generally, is obtained by the spin-coating of a solution of a polymeric material in a solvent and an evaporation of the solvent with a solid material, filling the via in the interlayer dielectric.
As the dimensions of the via and the interconnects continue to shrink with ongoing advances in semiconductor lithography, the limit of dimensions where the liquid is able to enter and fill the via is being reached due to the high liquid viscosity of the polymeric or oligomeric solution. In other words, the viscosity of the solution is sufficient, even if very low, to prevent the complete filling of extremely fine vias.
Further, the removal of the solvent through evaporation may also be detrimental to the structure, due to the high capillary forces involved. The increase in the aspect ratio of the features makes entry of the solutions into those features relatively difficult. In other words, when the via becomes sufficiently small, it is relatively hard to remove the solvent from the structure due to capillary forces and to get the solution into the structure because of capillary forces without damage to the features.
Thus, there is a need for better ways to fill relatively small dimension vias in advanced semiconductor processes.